• in-MRAM kmer matching accelerator
• NAND style ReRAM for processing in memory (bulk logic, neuromorphic processing, Tsetlin automata)
• NOR style ReRAM (this project includes design, manufacturing, bringup and testing of  a silicon chip) for processing in memory
• Processing in Gain Cell embedded DRAM
• NAND 5T Gain Cell Dynamic Content Addressable Memory 

Processing in commodity of the shelf (COTS) DRAM is a category of data-centric computing, an emerging alternative to classical von Neumann computer architecture  

We utilize the intrinsic analog properties of DRAM (such as charge sharing among several open cells) and apply modified timing to an UNMODIFIED COTS DRAM to implement logic Boolean function in- and using- DRAM arrays.

Current projects include

• Binary neuromorphic network (up to 64K neurons in parallel per DDR chip) 
• Tsetlin automaton acceleration (training and inference)
• Stochastic Ising machine
• Matrix multiplication 
• Genome classification using in COTS DDR binary neuromorphic neetwork

• Rad hard Hamming distance tolerant Content Addressable Memory (on silicon chip designed by EnICS and manufactured in commercial process)
• processing in Rad hard DDR for satellite and other high radiation environments 

• Memory augmented models 
• Advanced classification models for applications such as forest fire detection, algae movement detection etc.
• Autonomous agents