Patents | Prof. Joseph Shor

Prof. Joseph Shor is an inventor or co-inventor on more than 50 issued U.S. patents in analog circuit design, sensing, power management, hardware security, memory circuits, and semiconductor technologies.

Issued US Patents

Method for mitigation of droop timing errors including a droop detector and dual mode logic (2025)

Inventors: J. Shor, Y. Schifmann, I. Stanger, N. Shavit, E. R. Taco Lasso, A. Fish
U.S. Patent: 12,261,600
Date: March 25, 2025

Method to Utilize Mismatch Size to Produce Additional Stable Bit in Tilting PUF (2024)

Inventors: Y. Schifmann, J. Shor
U.S. Patent: 11,985,260
Date: May 14, 2024

Miniaturized digital temperature sensor (2021)

Inventors: O. Bass, J. Shor
U.S. Patent: 11,112,816
Date: September 7, 2021

Process monitor circuitry with measurement capability (2021)

Inventors: L. Lisha, J. Shor
U.S. Patent: 11,114,352
Date: September 7, 2021

Detecting Unreliable Bits In Transistor Circuitry (2021)

Inventors: J. Shor, Y. Weizman, Y. Shifman
U.S. Patent: 10,999,083
Date: May 4, 2021

Ring Oscillator Temperature Sensor (2021)

Inventors: J. Shor, N. Vinshtok-Melnik
U.S. Patent: 10,998,889
Date: May 4, 2021

Miniaturized Thermistor Based Thermal Sensor (2020)

Inventors: A. Mordakhay, J. Shor
U.S. Patent: 10,871,404
Date: December 22, 2020
https://patents.google.com/patent/US10871404/en

Two Bit/Cell SRAM PUF with Enhanced Reliability (2020)

Inventors: Y. Shifman, A. Miller, J. Shor
U.S. Patent: 10,848,327
Date: November 24, 2020
https://patents.google.com/patent/US10848327/en

Physical Unclonable Functions Related to Inverter Trip Points (2020)

Inventors: J. Shor, R. Levi, Y. Weizman
U.S. Patent: 10,630,493
Date: April 21, 2020
https://patents.google.com/patent/US10630493/en

Low Dropout Voltage Regulator Integrated with Digital Power Gate Driver (2018)

Inventors: K. Luria, A. Lyakhov, J. Shor, M. Zelikson
U.S. Patent: 10,156,859
Date: December 18, 2018
https://patents.google.com/patent/US10156859/en

Switch Capacitor in Bandgap Voltage Reference (BGREF) (2018)

Inventor: J. Shor
U.S. Patent: 10,061,336
Date: August 28, 2018
https://patents.google.com/patent/US10061336/en

Apparatus and Method for Selectively Disabling One or More Analog Circuits (2018)

Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor

Inventor: J. Shor
U.S. Patent: 9,996,143
Date: June 12, 2018
https://patents.google.com/patent/US9996143/en

Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor

Inventor: J. Shor
U.S. Patent: 9,996,143
Date: June 12, 2018
https://patents.google.com/patent/US9996143/en

Bandgap Reference Circuit with Low Output Impedance Stage and Power-On Detector (2018)

Inventors: J. Shor, G. Geannopoulos, F. Paillet, L. Vu, O. Dadashev
U.S. Patent: 9,921,592
Date: March 20, 2018
https://patents.google.com/patent/US9921592/en

Digital Phase-Locked Loop Supply Voltage Control (2018)

Inventors: N. Familia, A. Saksonov, E. Fayneh, J. Shor
U.S. Patent: 9,866,225
Date: January 9, 2018
https://patents.google.com/patent/US9866225/en

Accurate Power-On Detector (2017)

Inventor: J. Shor
U.S. Patent: 9,639,133
Date: May 2, 2017
https://patents.google.com/patent/US9639133/en

Digital Phase-Locked Loop Supply Voltage Control (2016)

Inventors: N. Familia, A. Saksonov, E. Fayneh, J. Shor
U.S. Patent: 9,350,365
Date: May 24, 2016
https://patents.google.com/patent/US9350365/en

Apparatus and Method for Selectively Disabling One or More Analog Circuits (2016)

Apparatus and Method for Selectively Disabling One or More Analog Circuits of a Processor During a Low Power State of the Processor

Inventor: J. Shor
U.S. Patent: 9,329,668
Date: May 3, 2016
https://patents.google.com/patent/US9329668/en

Apparatus and Method for Selectively Disabling One or More Analog Circuits of a Processor During a Low Power State of the Processor

Inventor: J. Shor
U.S. Patent: 9,329,668
Date: May 3, 2016
https://patents.google.com/patent/US9329668/en

Linear Voltage Regulator Based On-Die Grid (2015)

Inventors: F. Paillet, J. Shor, G. L. Geannopoulos, H. Y. Tan
U.S. Patent: 9,213,382
Date: December 15, 2015
https://patents.google.com/patent/US9213382/en

Ratio Meter for Temperature Sensor (2012)

Inventors: K. Luria, J. Shor
U.S. Patent: 8,136,987
Date: March 20, 2012
https://patents.google.com/patent/US8136987/en

Low Noise Voltage Regulator (2011)

Inventors: J. Shor, A. Zaidel, N. Familia
U.S. Patent: 7,973,518
Date: July 5, 2011
https://patents.google.com/patent/US7973518/en

Power Supply Circuit for a Phase-Locked Loop (2010)

Inventor: J. Shor
U.S. Patent: 7,728,688
Date: June 1, 2010
https://patents.google.com/patent/US7728688/en

Voltage Regulator (2009)

Inventors: J. Shor, E. Fayneh
U.S. Patent: 7,564,299
Date: July 21, 2009
https://patents.google.com/patent/US7564299/en

Analog Thermal Sensor Array (2009)

Inventors: K. Luria, J. Shor
U.S. Patent: 7,549,795
Date: June 23, 2009
https://patents.google.com/patent/US7549795/en

Bidirectional Body Bias Regulation (2008)

Inventors: J. Tschanz, V. Zia, V. De, J. Shor
U.S. Patent: 7,400,186
Date: July 15, 2008
https://patents.google.com/patent/US7400186/en

Buffered Cascode Current Mirror (2008)

Inventor: J. Shor
U.S. Patent: 7,336,133
Date: February 26, 2008
https://patents.google.com/patent/US7336133/en

MOS Capacitor with Reduced Parasitic Capacitance (2007)

Inventors: J. Shor, E. Maayan, Y. Betser
U.S. Patent: 7,256,438
Date: August 14, 2007
https://patents.google.com/patent/US7256438/en

Power-Up and BGREF Circuitry (2007)

Inventors: J. Shor, Y. Betser, Y. Sofer
U.S. Patent: 7,190,212
Date: March 13, 2007
https://patents.google.com/patent/US7190212/en

Charge Pump Element with Body Effect Cancellation for Early Charge Pump Stages (2006)

Inventors: J. Shor, E. Maayan
U.S. Patent: 7,148,739
Date: December 12, 2006
https://patents.google.com/patent/US7148739/en

Class AB Voltage Regulator (2005)

Inventors: J. Shor, Y. Betser
U.S. Patent: 6,922,099
Date: July 26, 2005
https://patents.google.com/patent/US6922099/en

Fast Discharge for Program and Verification (2005)

Inventors: J. Shor, Y. Polansky
U.S. Patent: 6,906,966
Date: June 14, 2005
https://patents.google.com/patent/US6906966/en

Operational Amplifier with Fast Rise Time (2005)

Inventor: J. Shor
U.S. Patent: 6,885,244
Date: April 26, 2005
https://patents.google.com/patent/US6885244/en

Charge Pump Stage with Body Effect Minimization (2005)

Inventors: J. Shor, E. Maayan, Y. Polansky
U.S. Patent: 6,864,739
Date: March 8, 2005
https://patents.google.com/patent/US6864739/en

Method and Circuit for Operating a Memory Cell Using a Single Charge Pump (2005)

Inventors: J. Shor, A. Harush, S. Eisen
U.S. Patent: 6,842,383
Date: January 11, 2005
https://patents.google.com/patent/US6842383/en

Stack Element Circuit (2004)

Inventors: J. Shor, E. Maayan
U.S. Patent: 6,791,396
Date: September 14, 2004
https://patents.google.com/patent/US6791396/en

Charge Pump Stage with Body Effect Minimization (2004)

Inventors: J. Shor, E. Maayan
U.S. Patent: 6,677,805
Date: January 13, 2004
https://patents.google.com/patent/US6677805/en

Charge Pump with Constant Boosted Output Voltage (2003)

Inventors: J. Shor, Y. Sofer, E. Maayan
U.S. Patent: 6,577,514
Date: June 10, 2003
https://patents.google.com/patent/US6577514/en

Voltage Regulator for Non-Volatile Memory with Large Power Supply Rejection (2002)

Voltage Regulator for Non-Volatile Memory with Large Power Supply Rejection Ration and Minimal Current Drain

Inventors: J. Shor, Y. Sofer, E. Maayan
U.S. Patent: 6,448,750
Date: September 10, 2002
https://patents.google.com/patent/US6448750/en

Voltage Regulator for Non-Volatile Memory with Large Power Supply Rejection Ration and Minimal Current Drain

Inventors: J. Shor, Y. Sofer, E. Maayan
U.S. Patent: 6,448,750
Date: September 10, 2002
https://patents.google.com/patent/US6448750/en

Circuit Arrangement to Compensate Non-Linearities in a Resistor, and Method (2000)

Inventors: J. Shor, V. Koifman, Y. Afek
U.S. Patent: 6,166,578
Date: December 26, 2000
https://patents.google.com/patent/US6166578/en

Method for Etching of Silicon Carbide Semiconductor Using Selective Etching (2000))(

Method for Etching of Silicon Carbide Semiconductor Using Selective Etching of Different Conductivity Types

Inventors: J. Shor, A. D. Kurtz, D. Goldstein
U.S. Patent: 6,034,001
Date: March 7, 2000
https://patents.google.com/patent/US6034001/en

Method for Etching of Silicon Carbide Semiconductor Using Selective Etching of Different Conductivity Types

Inventors: J. Shor, A. D. Kurtz, D. Goldstein
U.S. Patent: 6,034,001
Date: March 7, 2000
https://patents.google.com/patent/US6034001/en

Circuit with Hot-Electron Protection and Method (1999)

Inventors: J. Shor, M. Yosefin, D. Bruck
U.S. Patent: 5,963,076
Date: October 5, 1999
https://patents.google.com/patent/US5963076/en

Circuit with Hot Electron Protection and Method (1999)

Inventors: M. Yosefin, Y. Afek, J. Shor
U.S. Patent: 5,952,875
Date: September 14, 1999
https://patents.google.com/patent/US5952875/en

Apparatus and Method for Shifting Signal Levels (1998)

Inventors: J. Shor, E. Engel, N. Baron
U.S. Patent: 5,751,178
Date: May 12, 1998
https://patents.google.com/patent/US5751178/en

Method for Forming Isolated CMOS Structures on SOI Structures (1997)

Inventors: A. D. Kurtz, J. Shor, A. Ned
U.S. Patent: 5,597,738
Date: January 28, 1997
https://patents.google.com/patent/US5597738/en

Porous Silicon Carbide (SiC) Semiconductor Device (1996)

Inventors: J. Shor, A. D. Kurtz
U.S. Patent: 5,569,932
Date: October 29, 1996
https://patents.google.com/patent/US5569932/en

Method for Making Semiconductor Structures Having Environmentally Isolated Elements (1995)

Inventors: A. D. Kurtz, J. Shor, A. Ned
U.S. Patent: 5,461,001
Date: October 24, 1995
https://patents.google.com/patent/US5461001/en

Method of Fabricating Porous Silicon Carbide (SiC) (1995)

Inventors: J. Shor, A. D. Kurtz
U.S. Patent: 5,454,915
Date: October 3, 1995
https://patents.google.com/patent/US5454915/en

Semiconductor Structures Having Environmentally Isolated Elements and Method for Making ( 1995)

Semiconductor structures having environmentally isolated elements and method for making the same

Inventors: A. D. Kurtz, J. Shor, A. Ned
U.S. Patent: 5,386,142
Date: January 31, 1995
https://patents.google.com/patent/US5386142/en

Semiconductor structures having environmentally isolated elements and method for making the same

Inventors: A. D. Kurtz, J. Shor, A. Ned
U.S. Patent: 5,386,142
Date: January 31, 1995
https://patents.google.com/patent/US5386142/en

Fabricating Porous Silicon Carbide (1994)

Inventors: J. Shor, A. D. Kurtz
U.S. Patent: 5,376,241
Date: December 27, 1994
https://patents.google.com/patent/US5376241/en

Pressure Transducer Utilizing Diamond Piezoresistive Sensors and Silicon Carbide Force (1994)

Inventors: A. D. Kurtz, J. Shor
U.S. Patent: 5,303,594
Date: April 19, 1994
https://patents.google.com/patent/US5303594/en

Porous Silicon Carbide (SiC) Semiconductor Device (1994)

Inventors: J. Shor, A. D. Kurtz
U.S. Patent: 5,298,767
Date: March 29, 1994
https://patents.google.com/patent/US5298767/en

High Temperature Transducers and Methods of Fabricating the Same Employing Silicon Carbide (1994)

Inventors: A. D. Kurtz, D. Goldstein, J. Shor
U.S. Patent: 5,165,283
Date: November 24, 1992
https://patents.google.com/patent/US5165283/en