Prof. Joseph S. Shor received his Ph.D., M.Phil., and M.S. in Electrical Engineering from Columbia University and a B.A. in Physics from Queens College, CUNY. His early research focused on device physics, semiconductor materials, and high-temperature microsensors, including SiC-based sensing and fabrication technologies.

After moving to Israel, he transitioned to analog integrated-circuit design and held senior technical and leadership positions in the semiconductor industry. At Intel, he served as Principal Analog Engineer in the Microprocessor Products Group, developing analog circuits for advanced processor technologies, compact thermal sensors, power-management circuits, voltage regulation, and design methodologies for implementing analog circuits in digital CMOS processes. He also held senior positions at Saifun Semiconductor, Motorola Semiconductor Israel, and Kulite Semiconductor Products.

In 2015, he joined Bar-Ilan University and established the Analog Design Group in the Faculty of Engineering. His current research combines energy-efficient analog design, sensor interfaces, voltage and process monitoring, power management, circuit miniaturization, hardware security, novel memory circuits, and microsensors.

Columbia University — Ph.D., M.Phil., M.S. in Electrical Engineering
Queens College, CUNY — B.A. in Physics

2015–Present — Bar-Ilan University, Faculty of Engineering
2003–2015 — Intel Corporation
1999–2004 — Saifun Semiconductor
1994–1999 — Motorola Semiconductor Israel
1988–1994 — Kulite Semiconductor Products

Earlier research positions at Columbia University, IBM T. J. Watson Research Center, and the Technion

• EE Times Article "Dispelling the myth about analog scaling", based on ISSCC 2012 paper, Feb 2012.
• EE Times Article "Intel details Sandy Bridge at ISSCC", based on a ISSCC 2011 Paper, Feb, 2011.
• SBIR Program" 6H-SiC Pressure Sensors for High Temperature Applications"  was listed as an "SBIR Success Story"- 1996.
• NASA Certificate of Recognition for "Making SiC Semiconductor Devices Containing Porous Regions"- included in NASA Tech Briefs, 1996, based on SBIR Program.
• Trade Journal Note - "Porous SiC Expected to Yield Innovative Devices" in Technology Newsletter - "Electronic Design", Oct 24, 1996.
• Trade Journal Note – "6H SiC Pressure Sensors aim for High Temperature Operation at up to 600C" in Technology Breakthrough Section, "Electronic Design", Jan 6, 1997, based on SBIR.
• EE Times Article "Single chip answers base-station needs" – highlight from ICSPAT '96, Oct 17, 1996.
• Recipient of Kulite Scholarship – 1990 –Columbia University and Kulite Semiconductor.
• Paul Klapper Physics Prize – Queens College of CUNY, 1986

Affiliations And International Activities

• Associate Editor – Solid State Circuit Letters (2021 – present)
• Member ESSCERC Steering Committee (2022-present)
• Member ESSCERC Technical Program Committee (TPC) - Power Management Track-since 2018
  • Power Management Track Chair – 2024 – present.
  • Guest Associate Editor - Solid State Circuits Letters - ESSCIRC 2019 Special Issue.
  • Session Chair - "LDO Techniques", ESSCIRC 2018
• Member ISSCC International Technical Program Committee (ITPC) – International Solid State Circuits Conference, 2014-2018
• Guest Associate Editor - Journal of Solid State Circuits - JSSC - ISSCC 2017 Special Issue
• Session Co-Chair - ISSCC 2016 - Sensors and Displays
• Member of ISSCC 2014-2018 IMMD Subcommittee
• Member of ISSCC 2014-2018 European Regional Committee
• Member of ISSCC 2015 Demo Committee
• (ISSCC is the world's foremost Circuit/Analog International Conference)
• Senior Member IEEE
• Associate Editor - IEEE Sensors  2015-2024
• Member IEEE Solid State Circuits Society
• Member of American Institute of Physics
• Member – American Physical Society
• Reviewer for IEEE Journal of Solid State Circuits
• Reviewer for IEEE Transactions on Circuits and Systems 1
• Reviewer for IEEE Transactions of VLSI Systems
• Reviewer for IEEE VLSI Circuits Symposium
• Reviewer for Applied Physics Letters
• Reviewer for Materials Research Society
• Reviewer for ISCAS (International Conference of Circuits and Systems)
• Reviewer for Sensors Journal
• Reviewer for IEEE Access
• Reviewer for Microelectronics Journal
• Guest Editor in the 2014 Sensors Special Issue of the Journal of Low Power Electronics and Applications.
• IEEE FTFC 2014– Member of the Technical Program Committee.
• Member of Intel's International Circuit IP Patent Committee 2004-2015.
• Reviewer for the Intel International Design and Test Technology Conference 2013-2015
• Member of US Karate Team to Maccabia Games, 1985, 1981
• Member of Israel Traditional Karate Team, 2011, 2009.
• Certified Sports Coach and Instructor according to the Israel Sports Law

International And National Collaborations

1. Collaborated with many Intel groups in Portland and Folsom on the development of analog circuits for microprocessors. 2004-present.
2. NASA Lewis Research Center (now NASA Glenn) – Collaborated on the use of SiC for sensor and optoelectronic applications.  1989-1994.
3. Technion IIT, Dept. of Mats. Eng. – Collaborated with Prof. B.Z. Weiss (now deceased) – TEM characterization of the microstructure of Monocrystalline and Porous SiC. 1989-1994.
4. University of Pittsburg, Physics Dept. – Collaborated with Prof W.J. Choyke on the Luminescence properties of Porous SiC. 1992-1994.
5. Vanderbilt University, Dept. of Elec. Eng. – Collaborated with Prof. J. L. Davidson on the use of semiconducting diamond for sensors. 1992-94.