Chip Tapeouts | Prof. Joseph Shor

Since joining Bar-Ilan University, Prof. Joseph Shor has developed research infrastructure and trained students in the design and implementation of analog and mixed-signal integrated circuits. The group has completed numerous silicon tapeouts in advanced CMOS technologies, covering sensing, power management, hardware security, RF, biomedical circuits, and energy-efficient systems.

Pathfinder

May 2017 | TSMC 65 nm

This was the first BIU analog tapeout. It included thermal sensors, as well as PUF circuits. The circuits exhibited excellent functionality and have generated publications in JSSC, TCAS1, TCAS2, SSCL, and ESSCIRC.

Pathfinder2

May 2018 | 65nm TSMC

This follow-up tapeout included several new PUF circuits, all of which functioned well in Silicon. Papers were published in TCAS1, IEEE Access, OJCAS, CICC 2019, and ISCAS 2019.

Genesis

May 2019 | 65nm TSMC

This tapeout included PUFs, a Process Monitor and an ultra-low power bandgap reference.

SOC2

June 2019 | 16nm TSMC

Shor’s group participated in this tapeout of the Hiper Consortium and the contribution include an ultra-small, ultra-fast thermal sensor for thermal monitoring of the SOC. A paper was published in TVLSI.

Genesis2

Aug 2019 | 65nm TSMC

Circuits included a Ring-Oscillator based sensor, a mobility monitor and a Low Voltage Power-On-Reset Circuit. Papers were published in SSCL, ESSCIRC, TCAS2, OJCAS and IEEE Access.

Snir

Feb 2020 | 65nm TSMC

This chip contains an LDO, a Process Monitor, a Noise modeling circuit, two different Droop detector circuits, a Dual Mode Logic block (with Alex Fish group), and a Switch-capacitor DC-DC converter. Papers have been published in JSSC, IEEE Access, and ESSCIRC.